With the progress of transistor microfabrication processes, in recent years the operating frequencies of semiconductor integrated circuits have become higher and their sizes have become larger. In addition, currents which flow between power supplies and ground have become stronger and have made a sudden change. In these situations the influence of noise (such as simultaneous switching noise or radiation noise) caused by such currents is significant and effective measures to reduce noise are sought.
One of measures to reduce noise is a method for designing a clock tree so as to disperse clock skews in circuit sections in a semiconductor integrated circuit (skew dispersion method).
With the skew dispersion method, skews are produced for clock signals to be supplied to circuit sections to intentionally stagger times at which the clock signals reach the circuit sections and to disperse times at which the circuit sections operate. By going so, a current peak is lowered and noise is reduced.
The technique of extracting delay information from cell placement and routing information and increasing skews in a tolerance range of skew values calculated on the basis of the delay information was formerly proposed. With this technique, skew values for lowering the peak of a combined current obtained by combining on a time axis currents which flow through circuit blocks are found to suppress noise.
Japanese Laid-open Patent Publication No. 2000-267752
International Publication Pamphlet No. WO00/65651
However, noise contains plural frequencies. Accordingly, if a skew value is set, noise at some frequencies may be reduced. But on the contrary noise at other frequencies may increase. That is to say, it is difficult to adjust a clock skew for noise suppression.